A review of IC isolation technologies

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Author: Stanley Wolf
Date: Mar. 1992
From: Solid State Technology(Vol. 35, Issue 3)
Publisher: PennWell Publishing Corp.
Document Type: Article
Length: 1,938 words

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The techniques developed to isolate devices in integrated circuits each exhibit different attributes with respect to minimum isolation spacing, surface planarity, process complexity, and density of defects generated during fabrication of the isolation structure. Tradeoffs can be made among these characteristics when selecting an isolation technology for a particular circuit application. This article and those to follow in this series will survey isolation technologies and discuss the evolution of those which are even now being evaluated for submicron devices.

Before the invention of integrated circuits, only discrete diodes, bipolar transistors, and field-effect transistors (FETs) could be fabricated. In the early 1950s, these devices exhibited relatively high reverse-bias junction leakages and low breakdown voltage (caused by the large density of traps at the surface of single crystal silicon).

In 1958, Atalla and coworkers at Bell Telephone Laboratories found that when a thin layer of [SiO.sub.2] was grown on the surface of silicon where a pn junction intercepts the surface, the leakage current of the junction was reduced by a factor from 10 to 100. It was later understood that the oxide reduces and stabilizes many of the interface and oxide traps. Not only did such oxide-passivation of silicon surfaces allow diodes and transistors to be fabricated with significantly improved device characteristics, but the leakage path along the surface of the silicon was also effectively shut off. Thus one of the fundamental isolation capabilities needed for planar devices and integrated circuits had also been developed. In his report on the evolution of the MOS transistor, C.T. Sah remarks that the successful effort by the Bell Labs group to stabilize Si surfaces was the most important technological advance in microelectronics during the 1950s and that it blazed the trail that led to the development of the silicon integrated circuit [1].

The integrated circuit required electrical isolation between devices fabricated on the same piece of silicon. Bipolar ICs were the first to be developed and the method that evolved for isolating bipolar collector regions was termed junction isolation.

While PMOS and NMOS ICs of later vintage did not need junction isolation, an isolation structure that prevented parasitic channels between adjacent devices was still needed. The most important technique developed, LOCOS (LOCal Oxidation of Silicon), involved the formation of a semirecessed oxide in the nonactive (or field) areas of the substrate.

Eventually, bipolar/Cs adopted a similar LOCOS-isolation technology (with the oxide performing a somewhat different function than in MOS circuits). CMOS, when it arrived, also required that isolation regions exist between devices in adjacent tubs as well as between devices within each tub.

As device geometries reached submicron size, conventional LOCOS isolation technologies reached the limits of their effectiveness. Modified LOCOS processes (which overcome some drawbacks of conventional LOCOS for small geometry devices), trench isolation, and selective epitaxial isolation were among the newer approaches adopted. Table I traces the evolution and shows the expected trend of CMOS VLSI/ULSI process...

Source Citation

Source Citation
Wolf, Stanley. "A review of IC isolation technologies." Solid State Technology, vol. 35, no. 3, Mar. 1992, pp. 63+. Accessed 4 Dec. 2022.

Gale Document Number: GALE|A12308297